1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated circuit elements, such as MOS transistor structures, requiring contact areas to be formed after providing the interlayer dielectric material of a contact level.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently and in the foreseeable future, the majority of integrated circuits are and will be based on silicon devices due to the superior availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the immense number of transistor elements that may be necessary for producing complex integrated circuits, such as CPUs, memory devices, mixed signal devices and the like. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the current flow in a conductive channel positioned between the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length results in smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain extension regions and drain and source regions connecting thereto, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the source via the channel and to the drain region.
By providing sophisticated dopant profiles in the drain and source regions in combination with a reduced channel length, therefore, in total, a reduced series resistance of the transistors may be achieved. In sophisticated applications, however, the total resistance of transistors may no longer be determined by the drain and source regions and the channel region, but rather a contact resistivity may increasingly become a dominant factor, since with the reduction in size of the transistor elements, corresponding contact elements, which are to be understood as also containing elements extending through a dielectric material of a contact level of the semiconductor device, also may have to be accordingly adapted. In particular, the contact resistivity, i.e., the resistance of the transition area from the contact element to the highly doped drain and source areas, is typically reduced by forming a metal/silicon compound in the highly doped drain and source regions, which typically provides a lower resistance compared to even very strongly doped silicon material. To this end, appropriate silicidation processes have been developed, in which a refractory metal, such as cobalt, titanium and the like, is deposited and subsequently exposed to appropriate elevated temperatures in the range of 350-600° C. in order to initiate a chemical reaction between the silicon material and the refractory metal. The resulting resistance value of the silicon/metal compound strongly depends on the metal species and the process conditions. In recent developments, nickel is used as a preferred candidate for a metal silicide material due to its reduced resistivity compared to, for instance, cobalt silicide and the like. When forming a nickel silicide in the highly doped silicon regions, a nickel layer is typically formed, for instance, by sputter deposition, and subsequently a heat treatment on the basis of temperatures in the range of approximately 400° C. is applied, wherein an exposure to elevated temperatures in the further processing may be suppressed, since, in this case, the nickel silicide previously thermally stabilized on the basis of temperatures as specified above may otherwise exhibit reduced stability and/or increased resistivity.
In a typical process flow, the basic transistor configuration is completed after performing any high temperature processes and, thereafter, the nickel silicide may be formed on the basis of a process strategy as set forth above, wherein any non-reacted nickel material on dielectric surface areas may be efficiently removed on the basis of wet chemical selective etch recipes. Thereafter, the interlayer dielectric material system of the contact level is provided, for instance, by plasma enhanced chemical vapor deposition (CVD) techniques, in which typically process temperatures may be adjusted to a level that does not unduly affect the previously formed metal silicide. Thereafter, contact openings are formed in the interlayer dielectric material and are subsequently filled with an appropriate contact material, such as tungsten, which is typically provided, in combination with appropriate barrier materials, such as titanium, titanium nitride, on the basis of a thermally activated CVD process, wherein also in this case the applied process temperatures are compatible with the previously formed nickel silicide material.
Recently, sophisticated process strategies have been developed in which elevated temperatures may have to be applied in a very late manufacturing stage, i.e., after forming at least a part of the contact level, wherein these temperatures may not be compatible with the metal silicide formed in the doped semiconductor areas. For example, in sophisticated semiconductor devices, high-k metal gate electrode structures are frequently provided in order to overcome the limitations imposed by conventional silicon/polysilicon based gate electrode structures. To this end, a high-k dielectric material, such as hafnium oxide, hafnium silicon oxide, zirconium oxide and the like, may be provided as a gate dielectric material, possibly in combination with a very thin conventional silicon oxide based material, in order to reduce the gate leakage currents for a required capacitive coupling between the gate electrode and the channel region. Moreover, metal containing electrode materials may be provided in combination with the high-k dielectric material in order to endow these sophisticated gate electrode structures with superior conductivity and adjust an appropriate work function. Since generally fabrication of sophisticated high-k metal gate electrode structures requires a plurality of very complex process strategies, in some approaches, critical process steps, such as the incorporation of superior electrode materials, may be performed in a very late manufacturing stage, while the actual patterning and, thus, adjusting of the critical dimensions of the gate electrode structures may be accomplished on the basis of well-established gate materials, such as silicon dioxide and polysilicon. After completing the basic transistor configuration in these approaches, the interlayer dielectric material or at least a portion thereof is typically provided and the polysilicon of the gate electrode structures is then exposed on the basis of a removal process in order to enable the removal of the polysilicon material and the replacing thereof with appropriate metal-containing electrode materials. In some of these so-called replacement gate approaches, the incorporation of appropriate metal-containing materials may be associated with high temperature processes, for instance for appropriately incorporating work function metal species and the like, wherein the applied process temperatures may frequently not be compatible with the formation of a nickel silicide in an early manufacturing stage.
In particular due to restrictions imposed on the thermal budget of the silicidation process, process strategies have been developed in which the contact resistivity may be reduced in a later manufacturing stage, wherein a nickel silicide may be formed locally within the contact openings by forming a nickel layer in the contact opening and initiating the silicidation in accordance with well-established nickel silicide process recipes, followed by the removal of any excess metal. Thereafter, the contact metal may be formed by well-established process strategies, as discussed above.
This approach, which may also be referred to as a “late silicide process,” may provide superior process conditions, for instance in terms of any thermal budget of preceding manufacturing steps, however, the conventional process strategy described above may be associated with reduced reliability and electrical performance of the resulting contact level, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a semiconductor layer 102. The substrate 101 may typically be provided in the form of a silicon material or any other semiconductor material or insulating material, which is appropriate for forming thereon the semiconductor layer 102, typically a silicon-containing semiconductor material. Furthermore, a buried insulating material (not shown) may be provided below the semiconductor layer 102 if a silicon-on-insulator (SOI) architecture is considered. The device 100 is illustrated in an advanced manufacturing stage, i.e., in a manufacturing stage in which circuit elements 150 are formed in and above the semiconductor layer 102. As discussed above, in sophisticated applications, the circuit elements 150 may comprise transistors formed on the basis of critical dimensions of 50 nm and significantly less, for instance in sophisticated CMOS technologies. For example, the circuit elements 150 may be provided in the form of field effect transistors having components, such as gate electrode structures 151, with a lateral dimension 151L in the above-specified range. It should be appreciated that the circuit elements 150 including the components 151, such as gate electrode structures, may have any appropriate configuration in accordance with the corresponding design rules of the device 100. Furthermore, the semiconductor layer 102 in combination with the circuit elements 150 comprises highly doped regions 152, such as drain and source regions in the case of field effect transistors. In complex integrated circuits, device areas with closely spaced circuit elements, such as transistors in static RAM areas in complex CMOS devices and the like, may have to be implemented, thereby also requiring appropriate adapted contact elements in a contact level 120, which acts as an interface for connecting the circuit elements 150 with a complex metallization system (not shown) to be formed above the contact level. In the example shown, the contact level 120 may comprise an interlayer dielectric material 121, typically provided in the form of silicon dioxide, possibly in combination with an etch stop material 122, such as a silicon nitride material. Moreover, a contact opening 123 is formed in the dielectric materials 121, 122 so as to expose a portion of the highly doped region 152 in which, according to the “late” silicide process strategy, a metal silicide is to be formed within the contact opening 123 in order to reduce the overall resistivity of the circuit elements 150 when contacting the region 152. In some conventional approaches, the contact openings 123 are typically provided in the form of trenches that extend along a width direction, i.e., in FIG. 1a, a direction perpendicular to the drawing plane.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following conventional process techniques. The circuit elements 150 may be formed in appropriately defined semiconductor regions or active regions of the semiconductor layer 102, wherein a lateral delineation of any such semiconductor regions may be accomplished by providing appropriate isolation regions or structures (not shown). Thereafter, the circuit elements 150 may be formed, for instance, by incorporating an appropriate basic dopant species into the semiconductor layer 102, i.e., in the various active regions thereof, and forming appropriate materials and material systems in order to form the features 151, for instance in the form of gate electrode structures and the like. As discussed above, in sophisticated applications, very complex lithography and etch techniques may have to be applied so as to form the gate electrode structures in accordance with the overall requirements. Moreover, the highly doped regions 152 may be implemented at any appropriate manufacturing stage, for instance after forming the gate electrode structures 151, so as to obtain the highly doped regions 152 in a self-aligned manner. Thereafter, any high temperature processes may be performed in order to activate the dopant species, re-crystallize implantation-induced damage and the like. Next, a dielectric material of the contact level 120 may be formed, possibly in combination with sophisticated replacement gate approaches, as discussed above, wherein additional heat treatments may have to be carried out, as required for adjusting the overall transistor characteristics. In the example shown, the contact level may be formed by depositing the material 122, followed by the material 121, which is accomplished by applying well-established deposition recipes. Thereafter, the surface topography is planarized and complex lithography techniques are applied in order to pattern the material system of the level 120 in order to form the contact opening 123 with lateral dimensions corresponding to lateral dimensions of the circuit element 150.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a layer of refractory metal 103, such as a nickel layer in sophisticated applications, is formed on any exposed surface areas of the dielectric materials 121, 122 and thus within the contact opening 123. To this end, sputter deposition techniques may typically be applied, wherein, prior to the deposition of the material 103, typically sophisticated cleaning recipes are performed in order to appropriately prepare the exposed portion of the doped semiconductor region 152 for the subsequent silicidation process. Thereafter, a heat treatment 104 or a sequence of heat treatments may be performed, depending on the characteristics of the metal species in the layer 103, thereby initiating a diffusion of the metal species into the exposed semiconductor region 152, thereby increasingly forming a metal silicide therein. During the process 104, however, also a certain degree of diffusion may occur into the dielectric material 121, such as a TEOS-based silicon dioxide material, as indicated by 103A. In particular, in densely packed device regions requiring extremely scaled lateral dimensions of the contact elements, the presence of the metal species 103A in the dielectric material 121 may result in inferior reliability of the contact level and also electrical performance, such as parasitic capacitance and the like, may deteriorate.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage in which a metal silicide 153 is formed in the doped region 152, thereby reducing its contact resistivity for connecting to a contact element that is still to be formed in the contact opening 123. Furthermore, in this manufacturing stage, any non-reacted metal material is removed, which is typically accomplished on the basis of selective wet chemical etch recipes and the like. Thus, at surface areas of the dielectric material 121, the previously incorporated metal species 103A may still be present.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a contact element 124 is formed in the contact opening 123 and thus connects to the metal silicide region 153. The contact element 124 is typically comprised of a highly conductive metal, which at the same time is compatible with the overall device requirements and the further processing of the device 100. For example, in sophisticated applications, frequently a tungsten core metal 124A is provided in the contact openings 124 in combination with an appropriate barrier material or material system 124B, for instance provided in the form of titanium and titanium nitride and the like. The contact element 124 is typically formed by using appropriate deposition techniques, such as sputter deposition, for forming the one or more barrier layers 124B, followed by a sophisticated CVD process for depositing the tungsten material, wherein usually the barrier material system 124B may avoid undue exposure of any silicon dioxide materials to the CVD atmosphere for forming the tungsten material, which would otherwise result in a deterioration of the interface characteristics for many well-established tungsten deposition recipes. Thereafter, any excess material is removed, for instance by chemical mechanical polishing (CMP), thereby also removing the barrier material from above the dielectric material 121 of the contact level 120. Consequently, the contact element 124 is provided as an electrically isolated element.
As discussed above, upon further device scaling, the lateral dimension of the contact elements 124, at least in the horizontal direction in FIG. 1d, also has to be adapted to the reduced feature sizes of the circuit elements 150, thereby increasing the resistivity of the contact elements 124 for a given material system, in particular as the barrier material system 124B may not be arbitrarily reduced in thickness without jeopardizing the reliability of the contact elements 124. Moreover, as discussed above with reference to FIGS. 1b and 1c, the previously incorporated metal species 103A may also contribute to a reduced reliability and electrical performance of the contact elements 124, in particular in highly scaled semiconductor devices. In order to avoid the incorporation of the metal species 103A, it has, therefore, been suggested to form a diffusion blocking material, such as a silicon nitride liner, within the contact opening 123 prior to depositing the refractory metal species. Although this approach may significantly reduce any contact irregularities caused by the species 103A, on the other hand, the overall contact resistivity may increase since, for given lateral dimensions of the contact element 124, additional liner materials may result in a reduced volume that is available for the actual contact materials.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.